Py65 0.4 Released

  • Posted by Mike Naberezny in Hardware,Python

    Py65 0.4 has been released. Py65 provides tools for simulating hardware based on 6502-like microprocessors.

    Here are the highlights of this release:

    • We now support an additional microprocessor simulation: the 65C02. While still a work in progress, it is fairly complete and quite usable. It is based on the W65C02S microprocessor from the Western Design Center (WDC).
    • The monitor now supports assembling and disassembling the 65C02 opcodes. You can select the target microprocessor with the new mpu command.
    • There have been many other small additions and fixes to the monitor, the most useful of which is that most commands now have shortcuts such as d for disassemble.
    • A manual has been started and will be periodically published online. It is currently focused on the monitor usage.

    For a complete list of changes in this release, please see the changelog. Special thanks to Oscar Lindberg for making major contributions to this release.

    If you’re new to Py65, the README has an overview, installation instructions, and a link to the online documentation.

5 comments

  • comment by Matt Wilson 7 Jun 09

    I don’t mean to sound like a troll, but what do you do with a 6502 microprocessor?

  • comment by Mike Naberezny 7 Jun 09

    There are many applications for it in embedded systems and consumer devices. WDC’s website notes, “Annual volumes in the hundreds (100’s) of millions of units keep adding in a significant way to the estimated shipped volumes of five (5) to ten (10) billion units.”

    One of the Py65 contributors works professionally on a handheld device based on the ST20P64, a 65C02-based microcontroller with an integrated LCD controller and sound generator.

    There are quite a few specialty microcontrollers like that one compatible with the 6502 instruction set. This page has a few links to more. 6502-based cores are also popular in custom ASIC and VHDL designs, with even hobbyists synthesizing their own VHDL cores.

  • comment by Mark 15 Aug 09

    This is an excellent idea. Given the power of modern hardware it would be interesting to see the performance.

  • comment by Mark 16 Aug 09

    Answering my own quest. On my macbook pro (2.1GHz) I can execute

    ldy $0
    loop:
    iny
    jmp loop

    1 million steps in 20 seconds. I think the main loop is 5 cycles. Which is 250k cycles per second.

  • comment by mike.hazelett 30 Sep 14

    All I’m asking is where I can find a packrat 64 tnc I can get cheap.

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